A prior art in this technical field is described in IEEE Journal of Solid-State Circuits, SC-22 [3] (1987-6), page 437 to 441, "A New On-Chip Voltage Converter for Submicrometer High Density DRAM's". Its configuration will next be described with reference to the drawings.
FIG. 2 is a block diagram showing an example of configuration of internal voltage generating circuit having a conventional reference voltage generating circuit.
This internal voltage generating circuit comprises a reference voltage generating circuit 10 for producing a reference voltage Vref and an internal voltage driving circuit 20 responsive to the reference voltage Vref and supplying an internal voltage Vx to loads such as memory cell arrays.
The reference voltage generating circuit 10 is energized from a power supply voltage Vcc and is expected to produce a reference voltage Vref which is of a constant value irrespective of the fluctuations in the power supply voltage Vcc, the temperature Tj, and other environmental conditions, as well as the manufacturing variations in the parameters of the components. From the viewpoint of simplification of the fabrication process and cost reduction of the semiconductor device, it is desirable that the reference voltage generating circuit 10 be formed of MOS transistors and other MOS devices, and does not employ elements with other configurations or parameters (e.g., diodes or bipolar transistors).
The internal voltage generating circuit 20 comprises, for example, a differential amplifier operating responsive to the difference between the reference voltage Vref and the internal voltage Vx, and an output buffer responsive to the output of the differential amplifier and outputting the internal voltage Vx which is maintained constant and which can drive a large capacity, large current load.
FIG. 3 is a circuit diagram showing an example of configuration of the reference voltage generating circuit of FIG. 2. Its junction temperature-reference voltage characteristic is shown in FIG. 4.
As shown in FIG. 3, the reference voltage generating circuit 10 comprises a constant current source 11 configured for example of MOS transistors, and four serially connected N-channel MOS transistors 12a to 12d having their drain and gate commonly connected. The number of the NMOS transistors 12a to 12d can be varied to obtain the desired reference voltage Vref.
Since, in this reference voltage generating circuit, the drain and gate of each of the NMOS transistors 12a to 12d are commonly connected, all of the NMOS transistors 12a to 12d operate in the saturation region. For this reason, when a constant drain current is supplied to the NMOS transistors 12a to 12d, the variation in the drain voltage, i.e., the reference voltage Vref can be restrained over a wide range of fluctuation in the drain current because of the characteristics of MOS transistors.
The above described reference voltage generating circuit however had the following problems.
As shown in the junction temperature-reference voltage characteristics of FIG. 4, when the junction temperature of the NMOS transistors 12a to 12d increases, the reference voltage Vref output from the reference voltage generating circuit 10 decreases. When appropriate parameters are selected for the NMOS transistors 12a to 12d and the constant current source 11, the following relationship is obtained: EQU .DELTA.Vref/.DELTA.Tj=-0.0025[V/.C].
Assume that the reference voltage Vref exhibiting the characteristics of FIG. 4 is input to the internal voltage generating circuit 20, and the internal voltage Vx output from the internal voltage generating circuit 20 is applied to a power supply voltage terminal of a CMOS inverter in the load comprising a P-channel MOS transistor and an NMOS transistor connected in series. Since the MOS transistor drive current has a tendency to decrease with the temperature, when the junction temperature of the MOS transistor increases the voltage applied to the power supply voltage terminal of the CMOS inverter decreases, which lowers the speed of operation of the circuit in the CMOS inverter.
To prevent this, it may be contemplated to use, in place of the configuration of the reference voltage generating circuit of FIG. 3, a circuit configuration in which the reference voltage Vref is generated utilizing the forward voltage drop of a diode which is not dependent on the power supply voltage fluctuation. This however requires addition of process steps for the diodes to the fabrication of the ordinary semiconductor device fabrication process. This means the fabrication process has to be altered, the fabrication process is more complicated, and the fabrication cost is increased. This method was therefore not fully satisfactory.